Tutorial 4A: Measuring Setup Time of Flip-Flops using Parametric Simulation in Spectre

This material is by Steven Levitan and Bo Zhao for the environment at the University of Pittsburgh, 2008/2009.

·        Updated 6-Oct-2010 by Bo Zhao

 

We are using the NCSU/OSU FreePDK, Synopsys Design Compiler, Encounter 7.1, and Virtuoso 1.6.1.2

Please consult the NCSU EDA Wiki for background information

Many thanks to the team at NCSU  and Oklahoma State University for all their hard work!

Please see our tutorial on setting up the design environment and running Virtuoso  

 

This tutorial gives an example approach of measuring the setup time of a positive-edge flip-flop with a rising input. The same simulation approach can be utilized with appropriate changes for positive/negative-edge flip-flop setup/hold time measurements with rising/falling input.

 

1. Create a Test Bench Schematic

Build a testbench like the one below:

 


Notice that in this testbench:

 

(1)   There are names on all the wires of the signals that will be plotted. This helps you easily differentiate among them in the waveform plot.

 

(2)   The signals that come out of signal voltage sources are shaped by two FO3 inverters to make more realistic waveforms used to drive the flip-flop. To make the schematic clean, it is recommended that you use your existing inverters as instances to build the inverter chain.

 

(3)   A "vpulse" source is used to generate the periodic clock signal. It has rise/fall time of 50ps, a 2ns period, and thus a 950ps pulse width.

 

(4)   The input signal D is provided by a Piecewise Linear, "vpwl" source, also from the NCSU_Analog_Parts, which is a very flexible voltage source. We can build a signal by manually specifying the key points as time-voltage pairs for the waveform. It "draws" the waveform by connecting all these points one by one with straight lines.

 

NOTE: the best way to understand vpwl is by using it. Before reading the following parts of this tutorial, run some transient simulations with vpwl in ADE and see what it draws for you.

 

The vpwl waveform setup used here is shown below (click on the properties of the vpwl source to see this menu). We are drawing a rising edge which starts at time (2.1n - setup) and ends at (2.15n - setup). The actual time points will be decided by subtracting the value of the design variable "setup" from 2.1ns and 2.15ns during simulation. Here 2.1ns is simply an estimation of the beginning of the clock rising edge. So the point here is clear: first we line up the rising edges of D and clock, then we create a controllable delay t_DC (as "setup") between them. Also notice that the signal rise time equals: (2.15n - setup) - (2.1n - setup) = 2.15n-2.1n = 0.05ns.

 


 

2. Setup ADE for Basic Simulations

First we setup ADE to check the functionality of the flip-flop.

 

(1)   Create a tran simulation that stops at 4ns.

 

(2)   Add CLK, D and Q to the output plot list.

 

(3)   Click Variables -> Copy From Cellview to find "setup" as a design variable. Then give it a large enough value (e.g., 500ps).

 

The setup variable sets the time interval before the rising clock edge (which we have set to occur at 2.1ns) when the vpwl source will generate its rising edge.

 

The ADE window should now look like:

 

 


Run the simulation, the result should look like(without the white markers):

 


 

We set the signals such that the Flip-Flop caputures the “1” data value on the SECOND rising edge of clock. The first rising edge is needed to make a stable state on output Q prior to our measurement, since the flip-flop does not have a set or reset input to give it an initial value. Some important delays are marked on the graph in white. t_DC is the time between the D input changing and the Clock rising edge, this is the setup time that was used for this run. In order to find the “best” setup time for this flip-flop, the relationship between t_CQ and t_DC should be found. (See slide sets Lecture 10 and Chapter 7 from the older slide set) This is because the setup time not only defines the “legal” time for the input to change, but it also has an effect on the propagation delay of the flip-flop when it does change state.

3. Add Expression Outputs

The basic idea of a setup time parametric analysis simulation is based on the idea of sweeping t_DC and observing the induced t_CQ change. t_CQ can be quantified by evaluating its expression during every single simulation in the sweep. A tool called Calculator integrated in ADE can help writing such expressions that are understandable by the simulator. In the ADE window, click Tools -> Calculator and it will pop up as

 


 

First we add VOLTAGE signals CLK and Q to the Calculator. Click the bubble of "vt" on the top panel of Calculator; you will be switched to the schematic. Click on the wire named Q, then switch back to Calculator window, make sure VT("/Q") is in the white space below the top panel. Then click vt bubble again, manually switch to schematic, and click on the wire named CLK. Now there should be VT("/CLK") instead of the previous one.

 


 

Now both signals are added (although it seems like the latter just replaced the former). Then find "delay" in the list on the lower panel, click it. The list becomes a form named "delay".

 

 


 

We can see VT("/CLK") and VT("/Q") are already filled in as Signal 1 and 2. The following are evaluation options. For "Threshold Value", fill in 0.9 which is half the VDD we are using. "Edge Number" should be 2 for CLK and 1 for Q, "Edge Type" should be "rising". Because we are measuring the delay from the SECOND rising edge of CLK to the first rising edge of Q, please see the simulation plot shown above for a better understanding of what we are trying to accomplish. Leave other parts untouched, the Calculator window should look like the one shown in the figure.

 

Then click Ok, an expression is generated and displayed in the white space.

 


 

Next, leave the Calculator as it is and go back to ADE window. Click the "Setup Outputs" button on the right (4th from top).

 

In the new window, set "Name" as t_CQ. Then move the cursor to the "Expression" space, and click "Get Expression" button. The expression will be copied from Calculator and filled in.

 


 

Click Ok, and t_CQ are now added to the output list in ADE window.

 

NOTE on the sequence of signals:

For delay from CLK to Q, CLK should be Signal1 and Q should be Signal2 in the expression. However, when adding signals, we first click Q and then CLK on the schematic. This is because signals are actually pushed into a stack in the Calculator tool and the latter will be popped first as signal1 and the former second as signal2 when we use them. So always keep in mind the stack style that you will not get wrong sequences in the expression.

 

Although we have a design variable "setup" as a controllable D to clock delay, it is not the actual t_DC as the two inverter edge shapers add extra delay along the path. Use the same approach as we did for  t_CQ to add an expression for t_DC in the output list.

 

Run the simulation again. In addition to the plots, both t_CQ and t_DC are evaluated into values in the output list. Notice that there exists a difference between the values of t_DC and "setup".

 


4. Run Parametric Analysis

Now we can sweep the variable "setup" (to change t_DC) and directly plot t_CQ. Parametric Analysis is the most suitable tool for this job which can be launched by clicking Tools -> Parametric Analysis.

 

Specify the "Variable Name" to be "setup". Pick the range of analysis to be from "300p" to "0", and "Total Steps" to be "31". This means the simulation will run 31 times with step of 10ps. Or you can change "Step Control" to be "Linear Steps" and use "10p" as step size.

 


 

In the "Parametric Analysis" window, click Analysis -> Start. Two plots are generated once it is finished: Expressions and Transient Response:

 


 


 

t_CQ and t_DC vs. "setup" are plotted in "Expressions". t_DC has a linear wave with constant offset relative to "setup". The t_CQ wave rises slowly from large "setup" values and becomes steep from 150ps until 110ps. Below 110ps, t_CQ is relatively flat and its expression actually failed to be evaluated since in those cases there no longer exists a rising edge on Q. This is more observable in the "Transient Response" plot where all the signal waveforms are superimposed together. For instance, the wave called setup="100p";/Q  (click to highlight) keeps its low voltage through the second clock rising edge, which means the flip-flop failed to capture the value of D when "setup"=100ps. While when "setup"=110ps, the wave setup="110p";/Q rises after CLK, which implies a successful latching of the data.

 

However, 110ps is NOT the setup time we are looking for. Because:

 

(1)   t_DC is not exactly the same as the variable "setup". The markers show that the corresponding t_DC is 124ps. It is crucial to keep clear that the optimal flip-flop setup time should be extracted from the actual t_DC.

 

(2)   This sweep is too coarse-grained and we used it just for finding the approximate range of  the setup time. A fine-grained sweep with a much smaller time step should be performed around the approximate point ("setup"=110ps) for the precise value.

 

Finally, the simulated data should be exported to other tools that generate a t_CQ vs. t_DC plot.

 

5. Export Data for Plotting

Click the t_CQ wave to highlight it, then click the "Table" button on the toolbar (11th from left).

 


 

Make sure "Value" is selected, click OK. A table shows up with all the 31 values of "setup" and t_CQ listed.

 


 

Click File -> Save as CSV to save the data into a Comma-Separated Values file, which can be handled by many spreadsheet tools like Excel.

 

Don't forget to also export t_DC values!

 

An example Excel plot is shown below. It starts from the measured setup time, to the range where t_CQ becomes relatively constant.