Tutorial 5: Synthesis with Synopsys and Encounter
This material is by Steven Levitan and Bo Zhao for the environment at the
University of Pittsburgh, 2008/2009.
·
Updated
17-Feb-2010 by
Bo Zhao
We are using the NCSU/OSU FreePDK, Synopsys Design Compiler, Encounter 7.1, and Virtuoso 1.6.1.2
Please consult the NCSU EDA Wiki for background information
Many thanks to the team at NCSU and Oklahoma State University
for all their hard work!
Please see our tutorial on setting up the design environment and running Virtuoso
Before you get started, you should understand that these tools are very powerful and have lots of options. What we are showing here is one simple path through the design flow. To understand the tools, and their power, you must explore their capabilities by reading the help manuals, and trying lots of tests. Use the configuration files and scripts to keep your work manageable, and keep notes about what works, and what does not, so you don't make the same mistakes over and over.
Set up for Synthesis
Design Compiler is used for HDL synthesis. It reads in synthesizable Verilog or VHDL files and generates a cell-level netlist according to a standard cell library. In this tutorial, we are going to run Design Compiler in a script-based flow, so most work will be done automatically.
The library information is kept in a setup file in your root directory. As you may not have this file yet or your copy may be out-of-date, copy and rename the up-to-date setup file OSU.synopsys_dc.setup into your root directory.
> cp $CLASS/flow/synthesis/OSU.synopsys_dc.setup
~/.synopsys_dc.setup
Make a working directory and put the traffic light controller example in it.
> mkdir projects/traffic
> cd projects/traffic
> cp $CLASS/TrafficLight/*
.
Copy the script file dc_syn.tcl to your working directory. It's recommended that you give it the same name as your HDL file so that you will be clear about which script matches which module when your design grows to having more than one module.
> cp $CLASS/flow/synthesis/dc_syn.tcl
./traffic_light.tcl
Setup design environments.
> setup_all
You should see:
Cad set up as CAD_DIR = /CAD
Cadence set up as CDSHOME =
/CAD/cds/ic0612
Synopsys set up as
SYNOPSYS_ROOT = /CAD/synopsys/A-2007.12-SP5
Hspice set up as HSPICE_ROOT = /CAD/synopsys/hspice/hspice
Ciranova is set up as CNI_ROOT = /CAD/ciranova
OSU FreePDK
is set up as OSU_SOC = /CAD/ncsu/install_dir/FreePDK45/osu_soc
NCSU FreePDK
is set up as PDK_DIR = /CAD/ncsu/install_dir/FreePDK45/
Edit the file traffic_list.tcl to set the input files and clock pin to
match your design as shown below.
The top of this file shows the (only) design specific parameters. These will have to be changed again to run the script for other designs.
You can also take a new copy of the script from $CLASS/flow/synthesis/dc_syn.tcl
Now, Design Compiler is ready to go
With the script defined by trafficlight.tcl Synopsys Design Compiler will take the vhdl file and generate a “flat” verilog file that performs the same function, but only uses the logic gates in a specified design library.
Run Synopsys Design Complier: Type "dc_shell-t -f" followed by the .tcl file name.
> dc_shell-t -f traffic_light.tcl
This script will take several minutes and generate a lot of output to the screen starting with the information about the product:
And (if everything goes well) ending with:
You should now see a bunch of files in your directory:
DC_WORK TRAFFIC_LIGHT_SYN.v command.log timer.vhd traffic_light.vhd
DC_reports
alib-52
default.svf traffic_light.tcl
TRAFFIC_LIGHT.sdc cds.lib lib.defs
traffic_light.tcl~
When synthesis finished, you can find several files are generated. The _SYN.v file is the synthesized netlist in Verilog, it shares the same I/O ports as your original HDL while describing the design as which cells are used and the connections between them rather than behavior description. The .sdc file is the timing constraint file which is necessary for Place & Route. The .rep files in the DC_reports directory are reports of area, power, cell, etc.
Placement and & routing of the synthesized design
Placement and routing are the next steps of synthesis, often called "physical synthesis." In these steps the layout (or footprint) of the standard cells are placed on the surface of the chip, locating the cells such that cells that need to be connected are close to each other and the minimum total area is used. After placement, the cells are wired together by routing metal wires between them. This is done based on the connectivity represented in the netlist. This process is like taking the contents of a bowl of spaghetti (or a bowl of lo-mein 撈麵) and placing it on a checkerboard (or GO board, 围棋) organized to minimize the mess. The Cadence tool Encounter does this for us.
For this project you can use the same working directory as you did for synthesis, or you can copy the _SYN.v and .sdc file to a new working directory. If you use a new directory don't forget to setup design environments (run setup_all) if you have not done that.
Before we run Place & Route, we need to create our own design library in Cadence Virtuoso into which the placed & routed layout can be saved, so that it's ready for customization.
Start Virtuoso:
> virtuoso &
Click Tools -> Library
Manager...
Click File -> New -> Library...
Type the library name (ex: "test") and click OK.
In the pop up window, select "Attach to an existing technology library", click OK
Next, select "NCSU_TechLib_FreePDK45" and click OK
After that, your Library Manager should looks like:
Then, exit Virtuoso.
For more information about using Virtuoso, please refer to the earlier tutorials on the website.
Start Encounter
Cadence Design Systems SoC Encounter is used for Place & Route. Before
starting Encounter, we should first copy a configuration file which specifies
the library files to be used and some start-up settings.
> cp
$CLASS/flow/place_route/OSU.conf .
Then launch SoC
Encounter by typing "encounter".
> encounter
The Encounter window will pop up. Although we will do our work in the GUI window, you should always check the Terminal (where we start Encounter) for error messages after each step because all the information is only printed there.
Design Import
To begin, click Design --> Import Design...
In the Design Import window, click "Load...", then find the configuration file "OSU.conf" and click OK. You should then found that "Common Timing Libraries" and "LEF Files" are filled up. There are also some settings in the "Advanced" tab were set up by the configuration file, so you don't need to worry about that.
In the Design Import window, specify the Verilog Netlist file and the Timing Constraint File generated by synthesis, and the Common Timing Libraries and the LEF File from the CLASS directory. You can either let Encounter automatically recognize your top level design (select "Auto Assign"), or explicitly write in the top level design name (select "By User"). As shown below:
Any options that you change, you can save these options in a configuration file *.conf
click OK, your design is imported, and you can find the design status is "In Memory" at the top-right corner of the GUI window.
Specify Floorplan
Click Floorplan -> Specify Floorplan...
Specify by Size
Specify Core Size by Aspect Ratio
Set Ratio (H/W) to 1
Set Core Utilization to 0.7,
Set Core Margins by Core to IO Boundary
Set all the Core Margins to 20, then click OK
Click Floorplan
-> Connect Global Nets...
Here we need to add 4 connections. That is for each of Power and
Ground we need to bind the signal name to the pin name, and the signal name to
the meaning of "high" or "low" logic levels.
First, make sure "Apply All" and "Override prior connection" are checked. You need this for each connection.
Select "Pin" and set "Pin Name(s)" to vdd, set "To Global Net" to vdd.
Click Add to List
now Select "Tie High" and clear "Pin Name(s)"
Click Add to List
Now do both steps again for gnd (tying it LOW)
click Apply, then Check, then Close
Power Planning
Click Power -> Power
Planning -> Add Rings...
In the add rings window, the power and ground nets should already be there. Select
the same "H" (horizontal) metal layer for Top and Bottom ring, and
neighboring "V" (vertical) metal layer for Left and Right ring. For
example, for the Top and Bottom layer use metal 7, and then
you can use either metal 6 or metal
8 for the Left and Right layers.
Then, set all the Width and
Spacing to 5, and select "Center in channel" for
Offset, then click OK, as shown below. Note: clicking on
"update" will change the spacing.
At this point, the Encounter window should look like: