Tutorial 2: Generating Transistor I-V Curves with Spectre

This material is by Bo Zhao and Steven Levitan for the environment at the University of Pittsburgh, Fall 2008.

We are using the NCSU 1.6 Beta CDK and Virtuoso 1.6.1.2

Please consult the NCSU EDA Wiki for background information

Many thanks to the team at NCSU for all their hard work!

Please see our tutorial on setting up the design environment and running Virtuoso

Start the Cadence Design Framework

  • Start the Cadence Design Framework (virtuoso)

Create a New Schematic for this Exercise

  • Select the library you created before(Lab1)  in the Library Manager and select File->New->Cell View....
  • Call this new cell "Test_IV" create a schematic view

You can have many cells in a library and many views of each cell.

  • Use the steps from the previous tutorial to create a schematic like the one below:

 

NOTE we will not be synthesizing this circuit so we have broken our own rule and are putting the circuit and test_bench together in one schematic.

The schematic has one nmos4 transistor of length 180nm width 270nm. It has two vdc sources. One source is the vdd source set to 1.8 Volts, the other is the Vgs source and is set to the symbolic value of "vg" rather than a specific voltage. This is a "Design Variable" that we will set and use later.

  • Check and save this schematic
  • Launch ADE L
  • Open the "Choose Analysis" window, select "dc" and then check the box of "Component Parameter" in the "Sweep Variable" as shown below:

 

  • Click "Select Component" button, then go back to schematic and click the vdc component that is wired between the drain and source. A "Select Component Parameter" window  will appear
  • Select "dc" and click "OK," as shown below:

  • Go back to the "Choose Analysis" window and you will see that the "Component Name" and "Parameter Name" are already filled in.
  • In the "Sweep Range" area, write "0" in the "start" box and "1.8" in the "Stop" box, then click "OK".

 

  • In the ADE window, click Variables -> Copy From Cellview, you will see the vg variable is added to the "Design Variables" area on the left.
  • Double click the variable, in the new window, give a value of "1.8", then click "OK".

  • In the ADE window, click Outputs -> To Be Plotted -> Select On Schematic,
  • Click the drain (be careful that you click the red node precisely) and you can see the drain node is surrounded by a bubble, your ADE should now look like:

  • Click Simulation ->Netlist and Run, you will get a plot like

  • In the ADE window, click Tools -> Parametric Analysis.
  • In the "Parametric Analysis" window, specify the "Variable Name" to be "vg"
  • Pick the range of analysis to be from "0" to "1.8", and "Total Steps" to be "10".

This means the simulation will run 10 times with different "vg" value (0, 0.2, 0.4, ..., 1.6, 1.8) with step of 0.2.

  • In the "Parametric Analysis" window, click Analysis -> Start

You can see the simulation is running one by one with different "vg" values. Once it has finished, you should get a plot like this: